Emu10k1 Overview

Overview of the Emu10k1 Audio Signal Processor

Introduction

The Emu10k1 is a custom 32 bit fixed point digital signal processor with an instruction set geared towards audio effects. The Emu10k1 has instructions for handling both fractional as well as integer based fixed point arithmetic. The Emu contains a convention Multiply-Accumulate Core (MAC) as well as a Harvard Architecture such as those found in most commercial DSPs. The emu10k1 features a patented TANK (a.k.a TRAM) engine for handling delay lines and table lookups. A summary of the EMU10k1 specs are shown in the table below:

Fine print:This info has been collected form Patents, articles, and reverse-engineering (by others or myself ). I cannot guarantee that it is all correct. If you feel you have found a mistake please email me to inform me. Thanks.

Specifications

Parameter	Value	Unit
Sampling Rate	48000	Samples/sec
Instruction Execution Time	40.69	nsec
Instructions per Sample	512	Instructions
Program Memory Size	512	Instructions
Data Memory Size	256*4	bytes
Internal Tram Size	8k	samples (2 bytes/sample)
Int. Tram Maximum delay	170.667	msec
External Tram Size	up to 1	Mega Samples (2 bytes/sample)
Ext. Tram Maximum delay	21.84	sec

The Emu10k1 is sample locked, i.e exactly 512 instructions are executed per sample. Since no branch instruction are implemented, this guarantees that programs will maintain real-time execution.
Instructions always have 4 operands the values of which represent addresses of registers. The Memory map of registers is shown in the next section below.
Audio data on Tram delay lines are compressed down 16 bits. Tram is implement both on onboard ram, as well as host based ram (i.e. your PC).

Internal Memory Map [1]

Name	Address	Description
INPUTS
FX[0:15]	0x000 0x001 . . . . . . 0x00F
In0[L:R]	0x010 0x011	Analog recording source for AC97 Codec IC. Can be Cd, mic, etc.
In1[L:R]	0x012 0x013	S/PDIF CD digital in on card.
In2[L:R]	0x014 0x015	mic? - Unknown
In3[L:R]	0x016 0x017	LiveDrive -- TOSLink Optical In
In4[L:R]	0x018 0x019	LiveDrive -- Line/Mic In 1
In5[L:R]	0x01A 0x01B	LiveDrive -- Coaxial S/PDIF Input
In6[L:R]	0x01C 0x01D	LiveDrive -- Line/Mic In 2
Unknown	0x01D 0x01E	Unknown
OUTPUTS
Out0[L:R]	0x020 0x021	Front Analog Output
Out1[L:R]	0x022 0x023	LiveDrive -- TOSLink Optical Out
Out2[L:R]	0x024 0x025	Unknown
Out3[L:R]	0x026 0x027	LiveDrive -- headphone out
Out4[L:R]	0x028 0x029	Rear channel
Out5[L:R]	0x02A 0x02B	ADC recording buffer
Out6[L:R]	0x02C	microphone recording buffer
Unknown	0x02D . . . . . . 0x03f	Unknown or Unimplemented outputs
CONSTANTS
Constant	0x040	0x00000000
Constant	0x041	0x00000001
Constant	0x042	0x00000002
Constant	0x043	0x00000003
Constant	0x044	0x00000004
Constant	0x045	0x00000008
Constant	0x046	0x00000010
Constant	0x047	0x00000020
Constant	0x048	0x00000100
Constant	0x049	0x00010000
Constant	0x04a	0x00080000
Constant	0x04b	0x10000000
Constant	0x04c	0x20000000
Constant	0x04d	0x40000000
Constant	0x04e	0x80000000
Constant	0x04f	0x7fffffff
Constant	0x050	0xffffffff
Constant	0x051	0xfffffffe
Constant	0x052	0xc0000000
Constant	0x053	0x4f1bbcdc
Constant	0x054	0x5a7ef9db
Constant	0x055	0x00100000
Hardware Registers
Accumulator	0x056	67 bit wide accumulator
CCR	0x057	Condition Code Register
Noise Sources	0x058 0x059	Random number Generator-- Uniform distribution between -0.5 and 0.5 Uniform Frequency distribution Presumably both source are independent of each other.
Interupt Register	0x05A	Write to MSB to generate Interupt
Delay Base Address Counter	0x5B	See section on tram
Unknown Area	0x05C . . . . . . 0x05f	Unknown area
Unimplemented	0x060-0x0ff	Reserved/Unimplemented Area
General Purpose Registers (GPRs)
GPR	0x100 0x101 . . . . . . 0x102	General Purpose Registers
Tram Data Registers
ITRAM data registers	0x200 0x201 . . . . . . 0x27F	Internal Tram Data Access Registers
XTRAM data registers	0x280 0x281 . . . . . . 0x29F	External Tram Data Access Registers
unimplemented	0x2A0-0x2FF	Reserved/Unimplemented Area
Tram Address Registers
ITRAM data registers	0x300 0x301 . . . . . . 0x37F	Internal Tram Address Registers
XTRAM data registers	0x380 0x381 . . . . . . 0x39F	External Tram Address Registers
unimplemented	0x3A0-0x3FF	Reserved/Unimplemented Area

Condition Code Register

The 5 bit CCR has the following format:

Bits	31-5	4	3	2	1	0
Function	Don't Care	S	Z	M	N	B

S is set on Saturation
Z is set on zero
M is set on negative (Minus)
N is set on Normalized (MSB=previous MSB)
B is set on borrow

The CCR is set after each instruction based upon the Result of the instruction (R operand)

Accumulator

The Emu's accumulator is 67 bits wide. Multiplication of two 32 bit 2's-compliment numbers has at most a 63 bit result. This leaves 4 guard bits for sucessive MAC operations where intermediate instructions may overflow.

bits	66-64	62-31	31-0
name	guard bits	HIGH ACCUM	LOW ACCUM

yes, there is a 1 bit overlap between HIGH ACCUM and LOW ACCUM, this is normal.

Logarithmic Representation

The emu has the ability to convert values into a logarithmic representation, similar to floating point representation, but a bit more powerfull. The format follows the conventional sign-exponent-mantissa form, however the size of the exponent is variable. This allows a much wider range of numbers to be represented at the sacrifice of mantissa presision. The Logarithmic representation is best described in the section covering the LOG and EXP instructions which are used to convert from linear to log and back.[2]

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